Portapack-Carnage

◆ RCC_CFGR_PLLSRC_HSI_Div2 [4/4]

#define RCC_CFGR_PLLSRC_HSI_Div2   ((uint32_t)0x00000000)

#include <firmware/chibios/os/hal/platforms/STM32F30x/stm32f30x.h>

HSI clock divided by 2 selected as PLL entry clock source